Testing and reliable design of CMOS circuits

by Niraj K. Jha and Sandip Kundu

[目次]

  • 1. Introduction.- 1.1 What is Testing ?.- 1.2 Faults and Errors.- 1.3 Different Types of CMOS Circuits.- 1.3.1 Static CMOS Circuits.- 1.3.2 Dynamic CMOS Circuits.- 1.4 Gate-Level Model.- 1.5 Fault Models.- 1.5.1 Stuck-at Fault Model.- 1.5.2 Stuck-open Fault Model.- 1.5.3 Stuck-on Fault Model.- 1.5.4 Bridging Fault Model.- 1.5.5 Delay Fault Model.- References.- Problems.- 2. Test Invalidation.- 2.1 The Test Invalidation Problem.- 2.1.1 Test Invalidation due to Circuit Delays.- 2.1.2 Test Invalidation due to Charge Sharing.- 2.2 Robust Testability of Dynamic CMOS Circuits.- References.- Additional Reading.- Problems.- 3. Test Generation for Dynamic CMOS Circuits.- 3.1 Path Sensitization and D-Algorithm.- 3.2 Boolean Difference.- 3.3 Fault Collapsing.- 3.4 Redundancy in Circuits.- 3.5 Testing of Domino CMOS Circuits.- 3.5.1 Testing of Gates with Series-Parallel Network.- 3.5.2 Testing of Gates with Non-Series-Parallel Network.- 3.5.3 Testing of a General Circuit.- 3.5.4 Ordering of Test.- 3.6 Testing of CVS Circuits.- References.- Additional Reading.- Problems.- 4. Test Generation for Static CMOS Circuits.- 4.1 Non-Robust Test Generation.- 4.1.1 Test Generation from a Gate-Level Model.- 4.1.1.1 The Jain-Agrawal Method.- 4.1.1.2 The Reddy-Agrawal-Jain Method.- 4.1.1.3 The Chandramouli Method.- 4.1.2 Test Generation at the Switch Level.- 4.1.2.1 The Chiang-Vranesic Method.- 4.1.2.2 The Agrawal-Reddy Method.- 4.1.2.3 The Shih-Abraham Method.- 4.2 Robust Test Generation.- 4.2.1 The Reddy-Reddy-Agrawal Method.- 4.2.2 Some Issues in Robust Test Generation.- References.- Additional Reading.- Problems.- 5. Design for Robust Testability.- 5.1 Testable Designs Using Extra Inputs.- 5.1.1 The Reddy-Reddy-Kuhl Method.- 5.1.2 The Liu-McCluskey Method.- 5.2 Testable Designs Using Complex Gates.- 5.3 Testable Designs Using Parity Gates.- 5.4 Testable Designs Using Shannon's Theorem.- 5.4.1 Path Delay Faults.- 5.4.2 Robustly Testable Design.- References.- Additional Reading.- Problems.- 6. Self-Checking Circuits.- 6.1 Concepts and Definitions.- 6.2 Error-Detecting Codes.- 6.2.1 Codes for Detecting All Unidirectional Errors.- 6.2.2 t-Unidirectional Error-Detecting Codes.- 6.2.3 t-Burst Unidirectional Error-Detecting Codes.- 6.3 Self-Checking Checkers.- 6.3.1 Static vs Dynamic CMOS Implementations.- 6.3.2 Two-Rail Checkers.- 6.3.3 Parity Checkers.- 6.3.4 m-out-of-n Checkers.- 6.3.5 Berger Checkers.- 6.3.6 Checkers for Borden, Bose-Lin, Bose and Blaum Codes.- 6.3.7 Embedded Checker Problem.- 6.4 Self-Checking Functional Circuits.- References.- Additional Reading.- Problems.- 7. Conclusions.- References.

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この本の情報

書名 Testing and reliable design of CMOS circuits
著作者等 Jha, Niraj K.
Kundu, Sandip
Jha N. K.
シリーズ名 The Kluwer international series in engineering and computer science
出版元 Kluwer Academic Publishers
刊行年月 c1990
ページ数 xii, 231 p.
大きさ 25 cm
ISBN 0792390563
NCID BA09889761
※クリックでCiNii Booksを表示
言語 英語
出版国 アメリカ合衆国
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