Integrated circuit design

Neil H.E. Weste, David Money Harris

<P><B>For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers.</B></P><P><B> </B></P><P>The Fourth Edition of <I>CMOS VLSI Design: A Circuits and Systems perspective</I> presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce todayâ s most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels. </P>

「Nielsen BookData」より

[目次]

  • <P><B>Chapter 1</B> <B>Welcome to VLSI</B><BR>1.1 A Brief History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1<BR>1.2 Preview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6<BR>1.3 MOS Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6<BR>1.4 CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9<BR>1.4.1 The Inverter 9<BR>1.4.2 The NAND Gate 9<BR>1.4.3 CMOS Logic Gates 9<BR>1.4.4 The NOR Gate 11<BR>1.4.5 Compound Gates 11<BR>1.4.6 Pass Transistors and Transmission Gates 12<BR>1.4.7 Tristates 14<BR>1.4.8 Multiplexers 15<BR>1.4.9 Sequential Circuits 16<BR>1.5 CMOS Fabrication and Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19<BR>1.5.1 Inverter Cross-Section 19<BR>1.5.2 Fabrication Process 20<BR>1.5.3 Layout Design Rules 24<BR>1.5.4 Gate Layouts 27<BR>1.5.5 Stick Diagrams 28<BR>1.6 Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29<BR>1.6.1 Design Abstractions 30<BR>1.6.2 Structured Design 31<BR>1.6.3 Behavioral, Structural, and Physical Domains 31<BR>1.7 Example: A Simple MIPS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . 33<BR>1.7.1 MIPS Architecture 33<BR>1.7.2 Multicycle MIPS Microarchitectures 34<BR>1.8 Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<BR>1.8.1 Top-Level Interfaces 38<BR>1.8.2 Block Diagrams 38<BR>1.8.3 Hierarchy 40<BR>1.8.4 Hardware Description Languages 40<BR>1.9 Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42<BR>1.10 Physical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45<BR>1.10.1 Floorplanning 45<BR>1.10.2 Standard Cells 48<BR>1.10.3 Pitch Matching 50<BR>1.10.4 Slice Plans 50<BR>1.10.5 Arrays 51<BR>1.10.6 Area Estimation 51<BR>1.11 Design Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53<BR>1.12 Fabrication, Packaging, and Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54<BR>Summary and a Look Ahead 55<BR>Exercises 57<BR></P><P><B>Chapter 2 Devices</B><BR>2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61<BR>2.2 Long-Channel I-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64<BR>2.3 C-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68<BR>2.3.1 Simple MOS Capacitance Models 68<BR>2.3.2 Detailed MOS Gate Capacitance Model 70<BR>2.3.3 Detailed MOS Diffusion Capacitance Model 72<BR>2.4 Nonideal I-V Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74<BR>2.4.1 Mobility Degradation and Velocity Saturation 75<BR>2.4.2 Channel Length Modulation 78<BR>2.4.3 Threshold Voltage Effects 79<BR>2.4.4 Leakage 80<BR>2.4.5 Temperature Dependence 85<BR>2.4.6 Geometry Dependence 86<BR>2.4.7 Summary 86<BR>2.5 DC Transfer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87<BR>2.5.1 Static CMOS Inverter DC Characteristics 88<BR>2.5.2 Beta Ratio Effects 90<BR>2.5.3 Noise Margin 91<BR>2.5.4 Pass Transistor DC Characteristics 92<BR>2.6 Pitfalls and Fallacies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93<BR>Summary 94<BR>Exercises 95<BR></P><P><B>Chapter 3 Speed</B><BR>3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99<BR>3.1.1     Definitions 99<BR>3.1.2    Timing Optimization 100<BR>3.2 Transiet Response ...........................................................................................101<BR>3.3 RC Delay Model ...............................................................................................104<BR>3.3.1    Effective Resistance 104<BR>3.3.2    Gate and Diffusion Capacitance 105<BR>3.3.3    Equivalent RC Circuits 105<BR>3.3.4    Transient Response 106<BR>3.3.5    Elmore Delay 108<BR>3.3.6    Layout Dependence of Capcitance 111<BR>3.3.7    Determining Effective Resistance 112<BR>3.4 Linear Delay Model   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113<BR>3.4.1    Logical Effort 114<BR>3.4.2    Parasistic Delay 114<BR>3.4.3    Delay in a Logic Gate 116<BR>3.4.4    Drive 117</P><P>3.4.5    Extracting Logical Effort from Datasheets 117</P><P>3.4.6    Limitations to the Linear Delay Model 118<BR>3.5 Logical Effort of Paths  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121<BR>3.5.1    Delay in Multistage Logic Networks 121<BR>3.5.2    Choosing the Best Number of Stages  124<BR>3.5.3    Example  126<BR>3.5.4    Summary and Observations 127</P><P>3.5.5    Limitations of Logical Effort 129</P><P>3.5.6    Iterative Solutions for Sizing 129<BR>3.6 Timing analysis Delay Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131<BR>3.6.1    Slope-Based Linear Model 131<BR>3.6.2    Nonlinear Delay Model 132</P><P>3.6.3    Current Source Model 132<BR>3.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132<BR>3.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133<BR>Summary 134<BR>Exercises 134<BR></P><P><B>Chapter 4 Power</B><BR>4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139<BR>4.1.1 Definitions 140<BR>4.1.2 Examples  142</P><P>4.1.3 Sourches of Power Dissipation 142<BR>4.2 Dynamic Power. . . . . . . . . . . . . . . . . . . . . . . 143</P><P>4.2.1 Activity Factor 144</P><P>4.2.2. Capacitance 146</P><P>4.2.3 Voltage 148</P><P>4.2.4 Frequency 150</P><P>4.2.5 Short-Circuit Current 151</P><P>4.2.6 Resonant Circuits 151<BR>4.3 Static Powerl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152<BR>4.3.1 Static Power sources 152<BR>4.3.2 Power Gating 155<BR>4.3.3 Multiple Threshold Voltages and Oxide Thicknesses 157<BR>4.3.4 Variable Threshold Voltages 157<BR>4.3.5 Input Vector Control 158<BR>4.4 Energy-Delay Optimization ...........................................................................158<BR>4.4.1 Minimum Energy 158<BR>4.4.2 Minimum Energy-Delay Product 161<BR>4.4.3 Minimum Energy Under a Delay Constraint 161<BR>4.5 Low Power Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162<BR>4.5.1 Microarchitecture 162<BR>4.5.2 Parallelism and Pipelining 162<BR>4.5.3 Power Management Modes 163<BR>4.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164<BR>4.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165<BR>Summary 167<BR>Exercises 167<BR></P><P><B>Chapter 5 Wires</B><BR>5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169<BR>5.1.1 Wire Geometry 169<BR>5.1.2 Example:  Intel Metal Stacks 170<BR>5.2 Interconnect Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171<BR>5.2.1 Resistance 172<BR>5.2.2 Capacitance 173<BR>5.2.3 Inductance 176<BR>5.2.4 Skin Effect 177<BR>5.2.5 Terperature Dependence 178<BR>5.3 Interconnect Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178<BR>5.3.1 Delay 178<BR>5.3.2 Energy 180<BR>5.3.3 Crosstalk 180<BR>5.3.4 Inductive Effects 182<BR>5.3.5 An Aside on Effective Resistance and Elmore Delay 185<BR>5.4 Interconnect Engineering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187<BR>5.4.1 Width, Spacing and Layer 187<BR>5.4.2 Repeaters 188<BR>5.4.3 Crosstalk Contol 190</P><P>5.4.4 Low-Swing Signaling 192</P><P>5.4.5 Regenerators 194<BR>5.5 Logical Effort with Wires. . . . . . . . . . . . . . . . . . . . . . . ...................................194<BR>5.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195<BR>Summary 196<BR>Exercises 196<BR></P><P><B>Chapter 6 Scaling, Reliability and Variability</B><BR>6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199<BR>6.2 Variability             . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199<BR>6.2.1 Supply Voltage 200<BR>6.2.2 Termparature 200<BR>6.2.3 Process Variation 201<BR>6.2.4 Design Corners 202<BR>6.3 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204<BR>6.3.1 Reliability Terminology 204<BR>6.3.2 Oxide Wearout 205<BR>6.3.3 Interconnect Wearout 207<BR>6.3.4 Soft Errors 209<BR>6.3.5 Overvoltage Failure 210</P><P>6.3.6 Latchup 211<BR>6.4 Scaling             . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212<BR>6.4.1 Transistor Scaling 213<BR>6.4.2 Interconnect Scaling 215<BR>6.4.3 International Technology Roadmap for Semiconductors 216<BR>6.4.4 Impacts on Design 217<BR>6.5 Statistical Analysis of Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221</P><P>6.5.1 Properties of Random Variables 221</P><P>6.5.2 Variation Sources 224</P><P>6.5.3 Variation Impacts 227<BR>6.6 Variation-Tolerant Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232</P><P>6.6.1 Adaptive Control 233</P><P>6.6.2 Fault Tolerance 233</P><P>6.7  Pitfalls and Fallacies ..............................................................................................235</P><P>6.8 Historical Perspective ............................................................................................236<BR>Summary 242<BR>Exercises 242<BR><BR><B>Chapter 7 SPICE</B><BR>7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245<BR>7.2 A Spice Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246<BR>7.2.1 Souirces and Passive Components 246<BR>7.2.2 Transistor DC analysis 250<BR>7.2.3 Inverter Transient analysis 250<BR>7.2.4 Subcircuits and Measurement 252</P><P>7.2.5 Optimization 254</P><P>7.2.6 Other HSPICE Commands 256<BR>7.3 Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256<BR>7.3.1 Level 1 Models 257<BR>7.3.2 Level 2 and 3 Models 258<BR>7.3.3 BSIM Models 258<BR>7.3.4 Diffusion Capacitance Models 258<BR>7.3.5 Design Corners 260<BR>7.4 Device Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261<BR>7.4.1 I-V Characteristics 261<BR>7.4.2 Threshold Voltage 264<BR>7.4.3 Gate Capacitance 266<BR>7.4.4 Parasitic Capacitance 266</P><P>7.4.5 Effective Resistance 268</P><P>7.4.6 Comparison of Processes 269</P><P>7.4.7 Process and Environmental Sensitivity 271<BR>7.5 Circuit Characterization     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271<BR>7.5.1 Path Simulations 271<BR>7.5.2 DC Transfer Characteristics 273<BR>7.5.3 Logical Effort 273</P><P>7.5.4 Power and Energy 276</P><P>7.5.5 Simulating Mismatches 277</P><P>7.5.6 Monte Carlo simulation 277<BR>7.6 Interconnect Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277<BR>7.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280<BR>Summary 282<BR>Exercises 282<BR></P><P><B>Chapter 8 Gates</B><BR>8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285<BR>8.2 Circuit Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286<BR>8.2.1 Static CMOS 287<BR>8.2.2 Ratioed Circuits 292<BR>8.2.3 Cascode Voltage Switch Logic 297<BR>8.2.4 Dynamic Circuits 297<BR>8.2.5 Pass-Transistor Circuits 307<BR>8.3 Circuit Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312<BR>8.3.1 Threshold Drops 313<BR>8.3.2 Ratio Failures 313<BR>8.3.3 Leakage 314<BR>8.3.4 Charge Sharing 314<BR>8.3.5 Power Supply Noise 314</P><P>8.3.6 Hot Spots 315</P><P>8.3.7 Minority Carrier Injection 315</P><P>8.3.8 Back-Gate Coupling</P><P>8.3.9 Diffusion Input Noise Sensitivity 316</P><P>8.3.10 Process Sensitivity 316</P><P>8.3.11 Example:  Domino Noise Budgets 317<BR>8.4 Silicon-On-Insulator Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318<BR>8.4.1 Floating Body Voltage 319<BR>8.4.2 SOI Advantages 320<BR>8.4.3 SOI Disadvantages 320<BR>8.4.4 Implications for Circuit Styles 321<BR>8.4.5 Summary 322<BR>8.5 Subthreshold Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322<BR>8.5.1 Sizing 323<BR>8.5.2 Gate Selection 323<BR>8.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324<BR>8.7 Historical Perspective  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325<BR>Summary 327<BR>Exercises 328<BR></P><P><B>Chapter 9 Sequencing</B><BR>9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333<BR>9.2 Sequencing Static Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334<BR>9.2.1 Sequencing Methods 334<BR>9.2.2 Max-Delay Constraints 337<BR>9.2.3 Min-Delay Constraints 341<BR>9.2.4 Time Borrowing 344<BR>9.2.5 Clock Skew 347<BR>9.3 Circuit Design of Latches and Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349<BR>9.3.1 Conventional CMOS Latches 350<BR>9.3.2 Conventional CMOS Flip-Flops 351<BR>9.3.3 Pulsed Latches 353<BR>9.3.4 Resettable Latches and Flip-Flops 354<BR>9.3.5 Enabled Latches and Flip-Flops 355<BR>9.3.6 Incorporating Logic into Latches 356<BR>9.3.7 Klass Semidynamic Flip-Flop (SDFF) 357<BR>9.3.8 Differential Flip-Flops 357<BR>9.3.9 Dual Edge-Triggered Flip-Flops 358<BR>9.3.10 Radiation-Hardened Flip-Flops 359<BR>9.4 Static Sequencing Element Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360</P><P>9.4.1 Choice of Elements 361</P><P>9.4.2 Characterizing Sequencing Element Delays 363</P><P>9.4.3 State Retention Registers 366</P><P>9.4.4 Level-Converter Flip-Flops 366</P><P>9.4.5 Design Margin and Adaptive Sequential Elements 367<BR>9.5 Synchronizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......................................................369<BR>9.5.1 Metastability 370<BR>9.5.2 A Simple Synchronizer 373<BR>9.5.3 Communicating Between Asynchronous Clock Domains 374<BR>9.5.4 Common synchronizer Mistakes 375<BR>9.5.5 Arbiters 377</P><P>9.5.6 Degrees of Synchrony 377<BR>9.6 Wave Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378<BR>9.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380<BR>Summary 381<BR>Exercises 383<BR></P><P><B>Chapter 10 Datapaths</B><BR>10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387<BR>10.2 Addition/Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387<BR>10.2.1 Single-Bit Addition 388<BR>10.2.2 Carry-Propagate Addition 392<BR>10.2.3 Subtraction 416<BR>10.2.4 Multiple-Input Addition 416<BR>10.2.5 Flagged Prefix Adders 417<BR>10.3 One/Zero Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 419<BR>10.4 Comparators .............................. . . . . . . . . . . . . . . . . . . . . . . . . . . . 420<BR>10.4.1 Magnitude Comparator 420<BR>10.4.2 Equality Comparator 420<BR>10.4.3 <I>K=A+B Comparator </I>421<BR>10.5 Counters ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421</P><P>10.5.1 Binary Counters 422</P><P>10.5.2 Fast Binary Counters 423</P><P>10.5.3 Ring and Johnson Counters 424</P><P>10.5.4 Linear-Feedback Shift Registers 424<BR>10.6 Boolean Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426<BR>10.7 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426</P><P>10.7.1 Parity 426</P><P>10.7.2. Error-Correcting Codes 426</P><P>10.7.3. Gray codes 428</P><P>10.7.4. XOR/XNOR Circuit Forms 429<BR>10.8 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430</P><P>10.8.1 Funnel Shifter 431</P><P>10.8.2 Barrel Shifter 433</P><P>10.8.3 Alternative Shift Functions 434<BR>10.9 Multiplication .................................................................................................. . . . . . 434</P><P>10.9.1 Unsigned Array Multiplication 436</P><P>10.9.2 Two's Complement Array Multiplication 437</P><P>10.9.3 Booth Encoding 438</P><P>10.9.4 Column Addition 443</P><P>10.9.5 Final Addition 447</P><P>10.9.6 Fused Mulitply-Add 448</P><P>10.9.7 Summary 448</P><P>10.10 Parallel-Prefix Computations ..........................................................................................449</P><P>10.11 Pitfalls and Fallacies ......................................................................................................451<BR>Summary 452<BR>Exercises 452<BR></P><P><B>Chapter 11 Memories</B><BR>11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455<BR>11.2 SRAM ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456<BR>11.2.1 SRAM Cells 457<BR>11.2.2 Row Circuitry 464<BR>11.2.3 Column Circuitry 468<BR>11.2.4 Multi-Ported SRAM and Register Files 472<BR>11.2.5 Large SRAMs 473</P><P>11.2.6 Low-Power SRAMs 475</P><P>11.2.7 Area, Delay and Power of RAMs and Register Files 478<BR>11.3 DRAM ..................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480</P><P>11.3.1 Subarray Architectures 481</P><P>11.3.2 Column Circuitry 483</P><P>11.3.3 EMbedded DRAM 484<BR>11.4  Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485<BR>11.4.1 Programmable ROMs 487<BR>11.4.2 NAND ROMs 488<BR>11.4.3 Flash 489<BR>11.5 Serial Access Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491<BR>11.5.1 Shift Registers 491<BR>11.5.2 Queues (FIFO, LIFO) 491<BR>11.6 Content-Addressable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493<BR>11.7 Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495<BR>11.8 Robust Memory Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499<BR>11.8.1 Redundancy 499<BR>11.8.2 Error Correcting Codes (ECC) 501<BR>11.8.3 Radiation Hardening 501<BR>11.9 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501<BR>Summary 503<BR>Exercises 504<BR></P><P><B>Chapter 12 Packaging, Power, Clock, I/O</B><BR>12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507<BR>12.2 Packaging and Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507<BR>12.2.1 Package Options 507<BR>12.2.2 Chip-to-Package Connections 509<BR>12.2.3 Package Parasitics 510<BR>12.2.4 Heat Dissipation 510<BR>12.2.5 Temperature Sensors 511<BR>12.3 Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513<BR>12.3.1 On-Chip Power Distribution Network 514<BR>12.3.2 IR Drops 515<BR>12.3.3 L di/dt Noise 516</P><P>12.3.4 On-Chip Bypass Capacitance 517</P><P>12.3.5 Power Network Modeling 518</P><P>12.3.6 Power Supply Filtering 522</P><P>12.3.7 Charge Pumps 522</P><P>12.3.8 Sustrate Noise 523</P><P>12.3.9 Energy Scavenging 523<BR>12.4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524<BR>12.4.1 Definitions 524<BR>12.4.2 Clock System Architecture 526<BR>12.4.3 Global Clock Generation 527</P><P>12.4.4. Global Clock Distribution 529</P><P>12.4.5 Local Clock Gaters 533</P><P>12.4.6 Clock Skew Budgets 535</P><P>12.4.7 Adaptive Deskewing 537<BR>12.5 PLLs and DLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538<BR>12.5.1 PLLs 538<BR>12.5.2 DLLs 545</P><P>12.5.3 Pitfalls 547<BR>12.6 I/O.............................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548</P><P>12.6.1 Basic I/O Pad Circuits 549</P><P>12.6.2 Electrostatic Discharge Protection 551</P><P>12.6.3 Example:  MOSIS I/O Pads 552</P><P>12.6.4 Mixed-Voltage I/O 554<BR>12.7 High-Speed Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555</P><P>12.7.1 High-Speed I/O channels 555</P><P>12.7.2. Channel Noise and Interference 558</P><P>12.7.3 High-Speed Transmitters and Receivers 559</P><P>12.7.4 Synchronous Data Transmission 564</P><P>12.7.5 Clock Recovery in Source-Synchronous Systems 564</P><P>12.7.6 Clock Recoveryin Mesochronous Systems 566</P><P>12.7.7 Clock Recovery in Pleisochronous Systems 568<BR>12.8 Random Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568<BR>12.8.1 True Random Number Generators 568<BR>12.8.2 Chip Identification 569<BR>12.9 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570<BR>Summary 571<BR>Exercises 572<BR></P><P><B>Chapter 13 Methodology</B><BR>13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573<BR>13.2 Structured Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575<BR>13.2.1 A Software Radio-A System Example 576<BR>13.2.2 Hierarchy 578<BR>13.2.3 Regularity 581<BR>13.2.4 Modularity 583<BR>13.2.5 Locality 584</P><P>13.2.6 Summary 585<BR>13.3 Design Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585<BR>13.3.1 Microprocessor/DSP 585<BR>13.3.2 Programmable Logic 586<BR>13.3.3 Gate Array and Sea of Gates Design 589<BR>13.3.4 Cell-Based Design 590<BR>13.3.5 Full Custom Design 592<BR>13.3.6 Platform-Based Design-System on a Chip 593<BR>13.3.7 Sumary 594<BR>13.4 Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594<BR>13.4.1 Behavioral Synthesis Design flow (ASIC Design Flow) 595<BR>13.4.2 Automated Layout Generation 599<BR>13.4.3 Mixed-Signal or custom-Design Flow 60<BR>13.5 Design Economics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604<BR>13.5.1 Non-Recurring Engineering costs (NREs) 605<BR>13.5.2 Recurring Costs 607<BR>13.5.3 Fixed Costs 608</P><P>13.5.4 Schedule 609</P><P>13.5.5 Personpower 611</P><P>13.5.6 Project Management 611</P><P>13.5.7 Design Reuse 612<BR>13.6 Data Sheets and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613<BR>13.6.1 The Summary 613<BR>13.6.2 Pinout 613<BR>13.6.3 Description of Operation 613<BR>13.6.4 DC Specifications 613</P><P>13.6.5 AC Specifications 614</P><P>13.6.6 Package Diagram 614</P><P>13.6.7 Principles of Operation Manual 614</P><P>13.6.8 User Manual 614<BR>13.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615<BR>Exercises 615<BR></P><P><B>Chapter 14 Test</B><BR>14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617</P><P>14.1.1 Logic Verification 618</P><P>14.1.2 Debugging 620</P><P>14.1.3 Manufacturing Tests 622<BR>14.2 Testers, Test Fixtures and Test Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624<BR>14.2.1 Testers and Test Fixtures 624<BR>14.2.2 Test Programs 626<BR>14.2.3 Handlers 627<BR>14.3 Logic Verification Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628<BR>14.3.1 Test Vectors 628<BR>14.3.2 Testbenches and Harnesses 629<BR>14.3.3 Regression Testing 629<BR>14.3.4 Version Control 630<BR>14.3.5 Bug Tracking 631<BR>14.4 Silicon Debug Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631<BR>14.5 Manufacturing Test Principles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634<BR>14.5.1 Fault Models 635<BR>14.5.2 Observability 637<BR>14.5.3 Controllability 637<BR>14.5.4 Repeatability 637<BR>14.5.5 Survivability 637<BR>14.5.6 Fault Coverage 638<BR>14.5.7 Automatic Test Pattern Generation (ATPG) 638</P><P>14.5.8 Delay Fault Testing 638<BR>14.6 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639<BR>14.6.1 <I>Ad Hoc </I>Testing 639<BR>14.6.2 Scan Design 640<BR>14.6.3 Built-In Self-Test (BIST) 642<BR>14.6.4 IDDQ Testing 645<BR>14.6.5 Design for Manufacturability 645<BR>14.7 Boundary Scan..................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646<BR>14.8 Testing in a University Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647<BR>14.9 Pitfalls and Fallacies ......................................................................................................648</P><P>Summary 655</P><P>Exercices 655<BR></P><P><B>Chapter 15 Fabrication</B><BR>15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657<BR>15.2 CMOS Technologies  . . . . . . . . . . . . . . . . . . . . . . . . . . .................................658<BR>15.2.1 Wafer Formation 658<BR>15.2.2 Photolithography 659<BR>15.2.3 Well and Channel Formation 661</P><P>15.2.4 Silicon dioxide 663</P><P>15.2.5 Isolation 664</P><P>15.2.6 Gate Oxide 665</P><P>15.2.7 Gate and Source/Drain Formations 666</P><P>15.2.8 Contacts and Metallization 668</P><P>15.2.9 Passivation 670</P><P>15.2.10 Metrology 670<BR>15.3 Layout Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671<BR>15.3.1 Design Rule Background 671<BR>15.3.2 Scribe Line and Other Structures 674<BR>15.3.3 MOSIS Scalable CMOS Design Rules 675<BR>15.3.4 Micron Design Rules 676<BR>15.4 CMOS Process Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677<BR>15.4.1 Transistors 677<BR>15.4.2 Interconnect 680<BR>15.4.3 Circuit Elements 682<BR>15.4.4 Beyond conventional CMOS</P><P>15.5  Technology-Related CAD Issues ......................................................................688<BR>15.5.1 Design Rule Checking (DRC) 689<BR>15.5.2 Circuit Extraction 690<BR>15.6 Manufacturing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691<BR>15.6.1 Antenna Rules 691<BR>15.6.2 Layer Density Rules 692<BR>15.6.3 Resolution Enhancement Rules<BR>15.6.4 Metal Slotting Rules 693<BR>15.6.5 Yield Enhancement Guidelines 693<BR>15.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694</P><P>15.8 Historical Perspective ....................................................................................695<BR>Summary 697<BR>Exercises 697<BR></P><P>References 699<BR>Index 731<BR>Credits 751</P>

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この本の情報

書名 Integrated circuit design
著作者等 Harris, David Money
Weste, Neil H. E
Harris David
Weste Neil
出版元 Pearson
刊行年月 c2011
版表示 4th ed., Global ed
ページ数 xxiii, 751 p.
大きさ 26 cm
ISBN 9780321696946
NCID BB04763694
※クリックでCiNii Booksを表示
言語 英語
出版国 アメリカ合衆国
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